DSP Power Rails

This part is pretty self explanatory. The only thing to note is that USB1_VDDA18 and USB1_VDDA33 are disconnected because this design will not be using USB1.

 PMIC

So originally I didn’t plan on having the DSP have seperate power rails from the FPGA and the system at large. But as I worked through the design more and more it became clear that A) The amount of power rails was getting a bit ridiculous, and B) I really didn’t want to deal with trying to figure out different power sequences for both the FPGA and DSP on a combination of shared and not shared power rails. Most of the design above is adopted from the design that is used on the development board for the TMS320C6478. The only changes that were made were to the power sequencing (see next section) and changing some components around for some that are a bit easier to get or are cheaper.

The intent with this is to essentially adopt the design over to the FPGA so everything is set up in a way I just have to adjust a few resistor values (see the equations at the top of the image) and everything should be plug and play.

One thing to note is that Advisory 2.3.18 in the TMS320C6478 Silicon Errata talks about a condition that can cause the DSP to internally pull the 1.8V rail up to 2.7V when using I/Os at 3.3v. The last paragraph of section 1.1 in Texas Instruments document number SLVA490 gives a good summary of the issue as well as the recommended workaround. The workaround states that if you maintain sufficient bulk capacitance on the DVDD18 rail then it will not be able to pull up to 1.8V. In that same document the author decided based on calculations that 11.88uF was the capacitance needed to prevent it. See the references section at the bottom of the page for links to the documents that talk about this.